Hi,
how are you going to get +/- 0.1hz resolution with only 4 digits to display at 10mhz??

Scrolling? (=

For the higher frequencies, the circuits I've seen use a /16 counter and the internal counter/timers. I can't see why you need a pll or three counters.

In fact, the usage of internal counters (here: pins T0/T1/T2) is limited. There are two limits:

1) Maximum frequency. Standard C51 hardware requires 2 machine cycles (24 oscillator periods) to recognize 1-to-0 transaction correctly. So the maximum frequency which may be accepted via these pins is OSC/24. Using 12MHz cryctal it gives us only 500kHz. For 10MHz it needs with 240MHz crystal! :)

2) Duty cycle. Hardware requires that low level is held for at least one full machine cycle. So for example, even if input frequency is 100kHz but duty cycle is 1/20 (low level is produced only for about 500ns) then there is no warranty about correct work. Moreover it is even worse: sometimes it is recognized, another time it is not.

So, for high frequences it required to use external divider(s): it adjusts input frequence below limits and improves sygnal form to meandre.

Regards,
Oleg