You cannot always just pull the chip and put in a faster one and expect it to always work even if the crystal is the same and the F_osc to Bus Cycle divisor is the same.

A primary concern in this is the timing signals on the extenal bus interface if that is in use. The faster part will have shorter setup times, hold times, from the timing tables in the data sheet. Without going into specific details here I can think of several types of memory chip or peripheral interface chip design parameters that can fail muster when you evaluate worst case timing differences between the slow mode and faster chip mode.

So do not think that what the others have said that it is OK to pop out one chip and plug the other in. You really really need to redo the design analysis over again, as relates to the specific application on your board, to see if such a chip change is OK.

Michael Karas

PS - Mr Charles has done you the best service by telling you to beware of what you hear. I will tell you that you won't really know the answer till you dig into the data sheet and do the proper engineering analysis.
MJK