The data sheet clearly specifies a 12 MHz clock signal. The internal PLL of the chip turns this into a frequency 4 times higher. I don't think that any other clock rate will do, but you might want to try and see if you can get away with it.
The PLL cannot be influenced, but its output clock can be divided by a number which you can specify in the "clock division factor byte". I don't know what good that will do you if your base clock rate is not 48 MHz.
Maybe someone more up to speed with USB might fill in here?

Hans