Steve,

I don't know if your circuit will be sensitive to jitter. Digital PLL's exhibit much greater jitter than analog. I would hesitate to call this circuit a PLL. I doesn't lock phase, but it locks pulses per second. Instantaneous phase and frequency may be off by a great deal. Jitter can be minimized by driving the DPLL at a much higher frequency than is desired at the output. Designs such as 74HC297 are easily implemented in an FPGA.

Cory Spackman