Hello.
please if you have time read this.
by the way thanks to every one, i have checked program obj file and i have seen these things about the warning, its indecating with "REG BANK 0" as Oleg and Michael told.
i have seen 0020h is repeated about 5 times but it does not have the same variable.

i started the program with "org 0h" and this location used only to drive the motors.
again started with "org 18h: used for Monitor reserves Register Bank 3 (18 to 1F)
and "org 79h" for Monitor reserves Internal RAM 79 to 7F (Single-Step mode only)
but again i started with "org o" for Monitor reserves Flag F0 and Bit 20H (TXRDY).
i will post portion of the program where the problem seems to be, i tried to find out but i couldn`t.
TYPE BASE LENGTH RELOCATION SEGMENT NAME
-----------------------------------------------------

* * * * * * * D A T A M E M O R Y * * * * * * *
DATA 0000H 0080H ABSOLUTE
OVERLAP * REG 0000H 0008H ABSOLUTE "REG BANK 0"
OVERLAP * BIT 0020H.0 0000H.5 ABSOLUTE

* * * * * * * C O D E M E M O R Y * * * * * * *
CODE 0000H 057AH ABSOLUTE
would you tell me what does .5 means in overlap bit!!
and please take alook at this if you find some thing wrong let me know.


USER_RAM EQU 8000H ; Start of External RAM

USER_SIZE EQU 8000H ; External RAM size

DSEG

ORG 0

; These locations are only used by the Motor Drive Test programs

RHV: DS 1 ; RH Stepper value H
RLV: DS 1 ; RH Stepper value L
LHV: DS 1 ; LH Stepper value H
LLV: DS 1 ; LH Stepper value L
RS: DS 1 ; RH set speed
LS: DS 1 ; LH set speed
RTMPH: DS 1
RTMPL: DS 1
LTMPH: DS 1
LTMPL: DS 1
RCNT: DS 1
LCNT: DS 1
LDIST: DS 1
RDIST: DS 1
SQ: DS 1
RSQCNT: DS 1
LSQCNT: DS 1
TESTNO: DS 1

ORG 18H

; Monitor reserves Register Bank 3 (18 to 1F)

MPARAM: DS 2 ; Mem/Reg Pointer (r0,r1)

MADDR: DS 2 ; (r2,r3)
MI: DS 2 ; (r4,r5)

MBYTES: DS 1 ; (r6)

MINTEL: DS 1 ; Hex loader state (r7)

; Stack begins at 30H, builds upwards
; Monitor reserves Internal RAM 79 to 7F (Single-Step mode only)

ORG 79H

N1: DS 7

BSEG
; Monitor reserves Flag F0 and Bit 20H (TXRDY)

ORG 0
TXRDY: DBIT 1 ; Serial port Tx ready flag

IFLGR: DBIT 1 ; Only used by Drive Tests

IFLGL: DBIT 1 ; Only used by Drive Tests

LSTP: DBIT 1 ; Only used by Drive Tests

RSTP: DBIT 1 ; Only used by Drive Tests

CSEG
ORG 0
; System reset and interrupt vectors

RST: ajmp Reset ; Reset Vector

ORG 03H
EXI0: ljmp USER_RAM ; INT0 interrupt vector

ORG 0BH

T0I: ljmp USER_RAM+3 ; Timer 0 interrupt vector

ORG 13H

EXI1: ljmp USER_RAM+6 ; INT1 interrupt vector
ORG 1BH

T1I: ljmp USER_RAM+9 ; Timer 1 interrupt vector

ORG 23H

SERI: jbc RI, SIsvc ; Serial In interrupt?
jbc TI, SOsvc ; Serial Out ready?
reti

ORG 2BH

T2I: ljmp USER_RAM+12 ; Timer 2 interrupt vector

ORG 33H

PCAI: ljmp USER_RAM+15 ; PCA interrupt vector

Regards
Albarkani