Actualy when designing with fpgas you commonly find that the testbench takes more design work than the actual design that it is testing,mainly because you are trying to test for all possible failure mechanisms
When testeing you commonly do three different types of test,one is a behavioural test which simply tests that the logic works,the second converts the simple netlist into the actual physical parts on the fpga and tests that the stup and hold times dont break the logic which is where you suddenly see your nice simulation fill with all kinds of glitches,the third takes the timing delays from the physical placement of the parts on the fpga and tests that the delays dont break you logic, which is where you see your simulation fill with the most horrendous glitches which you are sure will break it.Then sometimes you might want to test what happens at lowest voltage and highest temperatures.If all those tests passs then yu can be fairly sure your design will work.