Thomas:
Most of the I2C devices on the bus do not need a reset. Only in rare occasions is it possible for a slave device to get left in a multi-byte read sequence. This can happen if either the master is reset and does not finish the multi-byte read sequence or if there is some kind of software bug in the master wherein it does not provide the NACK level to the slave during the 9th SCL pulse of the last byte transfer. In these cases the slave will stay on the bus preparing to perform the next transfer sequence.

When the master comes active after a reset of software upset it needs to do something about the possibly hung slave device. By clocking the SCL line up to 9 times the hung slave acts as if it is reading out the next byte. when it gets to the end of the supposed next byte it will release its SDA and look for a NACK to finish the multi-byte read.

This is what the "bus reset" sequence is all about.

Michael Karas