hi,

I think you know, that ports of 8051 when they are used as general input-output ones, may be considered as open-drain gate with pull-up resistor built-in (in fact, it is realized with some pFETs and nFET transistors but this is not a matter of question now).
So my point is: if one side of data line (here: C51) keeps this line at low state then another side of data line (RD+) cannot produce the one (high level) on this line.
I may suggest you to release data lines (set them to 0xFF) after each transaction. For example, next example is correct:

0) both RD+ and C51 write 0xFF to P1
1) RD+ clears D0 line:  11111110b   ; 0xFE
2) C51 clears D7 line:  01111110b   ; 0x7E
3) RD+ realeases D0:    01111111b
      and clears D1:    01111101b   ; 0x7D
4) C51 releases D7:     11111101b   ; 0xFD
5) RD+ releases D1:     11111111b   ; 0xFF

now goto 1)

With correct hardware, the example above should work.

Regards,
Oleg