Following the very interesting thread on the use of vertical counters for debouncing word-wide hardware inputs, I was prompted to some further thoughts on the subject.

The original thread can be found here:

http://www.8052.com/forum/rea...&top=76312

The original thread has long since fallen off the radar screen; I have taken the liberty of starting a new thread.

Essentially, the thought that occured to me was that - for various reasons - it is desirable for debounce counters to have quite a few bits. However, when implementing vertical counters of more than a very few bits, dealing with the carries each time the couters are incremented becomes a significant overhead.

An alternative to a counter is a Linear Feedback Shift Register (LFSR). A wide range of large maximum-length LFSRs can be constructed with just two feedback taps, this allows large vertical LFSRs to be constructed very simply. By using LFSRs rather than counters, debouncing using a large number of samples can be achieved very efficiently.

I have posted my ideas here:

http://www.programmersheaven.com/zone5/cat.../35789.htm