hi,

first of all, unlike RD2/IC2/ID2 devices, CC03 has ESPI bit as third bit of IEN1. This is because CC03 has CAN macro built-in which bit ETIM occupies IEN1.2 of. So you need do IE1 |= 0x08 to enable SPI interrupt.

Now, after transfer has been completed, the bit SPIF is set and it generates interrupt request. If you just leave ISR without clear this bit then program comes to ISR again and again. To clear SPIF bit you should read SPSTA and then SPDAT registers. For more details read page 127 of AT89C51CC03 manual (chapter "Master Mode").

Regards,
Oleg