Itried to add my controller to the code library but it didnt work so maybe is something craid has to wiggle with,anyway...
Just posted today(TRIED TO) the Beta release of the much delayed sdram controller for the 8052.
Handles address translation,refresh generation,precharging and activation for
pc100 speed rated sdrams.

Current device only handles single read/writes and is not pipelined so everything is very much relient on the 'done' signal.Its simple to change the state machine in sdramcnt.vhd to insert the correct number of NOPs in each sysle to implement the burst routines.
All constants to target the design at your particular sdram are in lib.vhd
Not had time to write any documentation but testbench.vhd shows how to drive theinterface using write_reg and read_reg procedures.

The device is targetted at xilinx fpga devices with DCM delay locked loops(spartan/virtex) as the sdram clock is driven by a delay locked loop with a feedback signal from the sdram clock pin to compensate for phase shifts due to pcb tracks.The uc_interface clock is running at the same speed as the sdram which is probably not what you want.dividing the master clock with a dll and using that as the processor clock springs to mind.

The sdram requires a 'long' initialisation delay before it is ready to be used which means simulations with a long initial period with nothing much happening fo don't be alarmed.
Its very much a work in progress with burst writing versions available soon so any bug reports all gratefully received.