Just posted first of a series of modifications to the high speed core found at http://www.e.kth.se/~e93_daw/vhdl/

Added a multiplier/divider removed the tristate busses for the ALU and added xilinx dual port ram.

Overall effects are a 3.5x increase in clock speed for the ALU.

Most synthesis tools will not instantiate a dual port ram so T51_pack_synth.vhd does that for you.

The multiplier can either be a generic macro or the on core 18 bit multiplier as found on the xilinx spartan/virtex FPGAs although the multiplier is not on the critical path for the ALU so this means that chosing th xilinx on-core multiplier only effects the overall size of the design.
More next week as I tackle the rest of the core logic.