??? 10/29/04 06:58 Read: times |
#79982 - Re: Enable INT0 only for one instruction Responding to: ???'s previous message |
hi,
SETB EX0 NOP CLR EX0By itself the above means little or useless. But maybe if viewed in context with rest of the code it MAY make sense - probably somebody knew exactly when a pulse will arrive at the INTO pin and had enabled it only just then? Raghunathan, The code above has clean mean - it enables external interrupt inside defined window only. EX0 is just a bit which enables/disables ISR vector call. The actual interrupt request bit is the IE0. By other words: you do not need to know exactly when a pulse arrives. Bit IE0 is set anyway if either falling edge has been detected or low level presents at the pin. (Bit IT0 is used to determine one of conditions above). The ISR of external interrupt 0 executes if the flag of its request is set and interrupt execution is allowed. For example, the external interrupt 0 edge detector caught the level transition on the pin /INT0 and set bit IE0. But bit EX0 is not set and as result, ISR of external interrupt 0 is not executed. And only when program runs through the code quoted above then the ISR is called. By the way, NOP is necessary instruction here. Because SET EX0 modifyes IE register, so one more instruction will be executed before any interrupt is vectored to. Inserting NOP allows external interrupt 0 to be executed. Regards, Oleg |
Topic | Author | Date |
Re: Enable INT0 only for one instruction | 01/01/70 00:00 | |
Re: Enable INT0 only for one instruction | 01/01/70 00:00 | |
Re: Enable INT0 only for one instruction | 01/01/70 00:00 | |
Re: Enable INT0 only for one instruction | 01/01/70 00:00 | |
Missed the point...![]() | 01/01/70 00:00 | |
Re: Enable INT0 only for one instruction | 01/01/70 00:00 |