hi,

SiLabs 'F00x, 'F01x and 'F02x have a SPI transferring arbitrary bits (1-8) as a master.

Indeed these parts might be used. Just next thing should be took in consideration:
original poster requires with bitrate 19kbs (19200?) and so it defines SYSCLK as

fsys = fspi *2*[1..256];

From this, max SYSCLK may not be more than ~10MHz.

From other side, software-made shift register does not limit derivative select.

Regards,
Oleg