... and changed, as I was curious, how the different architectures cope with reduction of the clocks per cycles.

I found a couple of interesting things:
- there are "fully conforming" cores which only reduced the clocks-per-instruction-cycle (the RD2 2x, uPSD 3x and LPC 6x); so for these the "normal" cycle counting might apply (except for the uPSD, where branch cache misses might change the things - unfortunately it is not too clearly described in the datasheet).
- I assumed that those manufacturers who produced improved 4clock cores and them moved to 1clock (Dallas and Goal), would have the same instruction-cycle count (just with less clocks per cycle). They have not.
- although the LPC9xx is a 2-clock architectore, it's maximum clock is surprisingly slow, which makes it not-so-fast at the end of the day. I assume, this is only a technological issue and they will go higher (I think the new 901x are already a bit faster, am I right?).

You can download the excel chart if you want, then multiply the number of instruction cycles by the number of clocks per instruction cycle; hence you will get the clocks/per/instruction table. This is the way how the "benchmark's" results are calculated (you will find both instruction cycles and oscillator clocks at the summary).

Jan Waclawek


PS. And, of course, there might be errors, I was typing this in from datasheets during the nights - please let me know if you find some.