There's one problem with this, which is that you need to reset the flop after you use the edge. It is useful if you need to latch the edge-detected state.

In a synchronous system, it's better to simply run the input into the D input of a flop. The system clock is used to clock the flop. The edge detection logic is simple (Verilog notation):

assign rising_edge = D && ~Q;

where D is the flop's D input, and Q is its output.

A metastable-safe version of this is to synchronize the input using one flop and then run that Q output into the D input of another flop. Then, you use the output of both flops for your edge detect:

assign rising_edge = Q1 && ~Q2;

where Q1 is the output of the first flop, and Q2 is the output of the second.

If you're looking for the falling edge, just change this to:

assign falling_edge = ~Q1 && Q2;

You'll see the signal rising_edge (or falling_edge) asserted for exactly one clock tick.

The rest of your logic determines whether a one-tick strobe is useful, or whether you need to latch that detected state and clear it with some other logic. All basic stuff, all real easy.

-a