??? 03/29/05 15:54 Read: times Msg Score: +1 +1 Informative |
#90607 - How I address this problem... Responding to: ???'s previous message |
I have implemented such system on several microcontrollers where the routine that writes to FLASH must be in the SRAM. Of course that assumes that the microcontroller can execute code from internal SRAM which of course is NOT something a typical '51 style of processor can perform.
What I have done is to make the boot loader function in ASSEMBLER as the block of memory that encapsulates the interrupt vectors. Then at re-programming time I do not permit the block of FLASH where the boot loader is located to get erased or re-programmed. This is an essential requirement for reliability if power disruption should occur during the programming process. The part of the code that is moved to SRAM for execution is limited to just the short subroutine that performs a FLASH block erase or a write. This scheme requires also that you have enough RAM to store the erase/write routine and a buffer of size suitable to pass the required size write record to the FLASH write routine. Note that if your hardware setup is unable to support this minimum set of capabilities, or if it is one that all of FLASH erases as a single block, then I would strongly suggest that you look at other hardware options. There are far too many really nice platforms that support sectorized FLASH and execute-while-write type flash that it is unnecessary to stay trapped with older style solutions that make IAP very hard and unreliable. Michael Karas |
Topic | Author | Date |
Boot loader with single flash | 01/01/70 00:00 | |
this is a '51 forum not M16C | 01/01/70 00:00 | |
How I address this problem... | 01/01/70 00:00 | |
My Question is generic not for M16C | 01/01/70 00:00 | |
I said what you have to do.... | 01/01/70 00:00 | |
will try in Assembly but..... | 01/01/70 00:00 | |
Don't bother with 'C' | 01/01/70 00:00 | |
one caveat![]() | 01/01/70 00:00 |