it was limited in features but quite reliable.

There is "limited" and the there is "limited".

If your tool is too limited, you are better off with no tool.

absolute requirements for an ICE (that I think of now):
* if no breakpoints the code runs as if no ICE there.
* all I/O have the same timing and shape as a if regular chip was inserted
* breakpoints can be set in C source
* breakpoints can be set in disassembled C source
* breakpoints can be set in assembly source
* variables can be displayed by name
* all registers and SFRs can be displayed by name
* all memory areas can be displayed
* reasonably fast download of code
necessary, but missing in SILabs, is there in Ceibo
* single stepping in C (not in disassembled C)


nice, but (in my opinion) not necessary
* conditional breakpoints (e.g. break here only if r0 = 7)
* trace
* built in variable oscillator

I am sure the above is reasonably, but probably not totally, complete it represent what vcomes to mind in 3 minutes.

Erik