Based on the following extracts from 'Bible', I'm about to omitt the pull-ups on p0 in my 89s52 system (programmed by a separate programmer) where only some SRAM is put on p0 and nothing else. Am I missing something?

Port 0 differs in that its internal pullups are not active during normal
port operation. The pullup FET in the P0 output driver (see Figure 4)
is used only when the port is emitting 1s during external memory
accesses. Otherwise the pullup FET is off. Consequently P0 lines
that are being used as output port lines are open drain. Writing a 1
to the bit latch leaves both output FETs off, so the pin floats. In that
condition it can be used as a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pullups, they are
sometimes called “quasi- bidirectional” ports. When configured as
inputs they pull high and will source current (IIL, in the data sheets)
when externally pulled low. Port 0, on the other hand, is considered
“true” bidirectional, because when configured as an input it floats.

Port 0 output buffers can each drive 8 LS TTL inputs. They do,
however, require external pullups to drive NMOS inputs, except
when being used as the ADDRESS/DATA bus for external memory.

In any case, the low byte of the address is time-multiplexed with the
data byte on Port 0. The ADDR/DATA signals drive both FETs in the
Port 0 output buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do not require external pullups. ALE
(Address Latch Enable) should be used to capture the address byte
into an external latch. The address byte is valid at the negative
transition of ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is activated, and remains there
until after WR is deactivated. In a read cycle, the incoming byte is
accepted at Port 0 just before the read strobe is deactivated.

Port 0: Port 0 is an 8-bit open drain bidirectional port. As an open
drain output port, it can sink eight LS TTL loads. Port 0 pins that
have 1s written to them float, and in that state will function as high
impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external memory. In this application
it uses strong internal pullups when emitting 1s. Port 0 emits code
bytes during program verification. In this application, external pullups
are required.