Hello ,

I am currently working with Cygnal's C8051F022....I am using the Port 0 for serial communication

My F022 acts as the SPI master.

My SPI is intialized as follows:


mov p0mdout,#015h ( port configuration)
( this is to enable p0.0(TX),P0.2(SCK) and p0.4(MOSI) as push-pull outputs.)



mov spi0cn,#003h ;SPI Control Register
mov spi0cfg,#007h ;SPI Configuration
Register
mov spi0ckr,#063h ;SPI Clock Rate
Register

(this is to configure SPI0 for 8-bit, 172.8 khz SCK,Master mode, data sampled on 1st SCK rising edge)


My sysmtem clk is intialized as follows:(22.1184 Mhz)

mov oscxcn,#067h ;External Oscillator Control
Register
clr a ; osc
djnz acc,$ ; wait for
djnz acc,$ ; at least 1ms

ox_wait:
mov a,oscxcn
jnb acc.7,ox_wait ;poll XTLVLD

mov oscicn,#008h ;Internal Oscillator Control
Register

As far as I know, these are initialized correctly

So there should be an SCK output at P0.2...but there isnt

I dont understand where i am goin wrong..

I am transferring an 8 bit data from the F022 to another slave device..


I have the register R7 whose value changes from time to time.
Every time its value changes, I need F022 to transfer one 8 bit direct value to the slave followed by the 8 bit value of R7.

How can I do this in ASM?

I have tried doing this as follows:
mov spi0cn,#003h
mov spi0cfg,#007h
clr fpga_cs_1
mov spi0dat,#11h
wait_here1:
jnb spi0cn.7,wait_here1
clr spi0cn.7
setb fpga_cs_1
clr fpga_cs_1
mov spi0dat,R7
wait_here2:
jnb spi0cn.7,wait_here2
clr spi0cn.7
setb fpga_cs_1
ret

I am not sure if this is doing it right..

Any ideas or suggestions about this?

Any help is greatly appreciated.

Thank you,

Mahathi