Hi guys,
I've been up 36 hours straight trying to get a handle on what's going wrong with my PCA ISR. I'm hoping one of y'all might have encountered this situation before.

I'm running a SiLabs 'F120 at 88MHz, and using SYSCLK as the PCA timebase. I have one input, CEX4, configured in edge-triggered capture. Both CCF4's and CF's interrupts are enabled.
I need to create a pseudo-24-bit counter (actually for 4 channels, but I'm starting with one).

I am using two debug pin outputs to a logic analyzer to figure out my proble, which is this:

I have the following code in my module ISR:


I have the PCA configured as a high-priority interrupt. My only
other interrupt is UART0, which is low priority, and inactive unless I send it a command.

I also set up a 16-bit PWM output on CEX5, which works fine. No interrupt configured for it.

Module CEX4 receives a tachometer PWM-like signal whose period is coincidentally close to the time required to overflow the PCA counter. What appears to be happening is that the DEBUG output transitions on overflows as expected - it lines up perfectly with the PWM period. However, when the tachometer moves into the time domain where the overflow is expected,the DEBUG 1 output still occurs where I expect it to, but the DEBUG output does not toggle when the CCF4 input appears to coincide with its expected appearance. I am expecting the PCA interrupt to reoccur occur once I leave the ISR if the overflow occurs after I've had a chance to read it by the pca_irq_flags assignment, yet that particular interrupt is missed. It happens very infrequently, but I can't tolerate any misses of updates to the timer_ov variable. Am I thinking about something incorrectly?

Kevin