The best solution is using PLD (better will be a fgpa) to interface your micro controller with SDRAM.

Choose a PLD with some RAM block which is used as DPRAM (dual port ram).

Then, built a cache system (to prefetch data from SDRAM with any size of the bus) Then the conversion of 8bit<->64bit (please note it exists SDRAM with 16bit or 32bit data bus) will be made through internal DPRAM. Furthermore, the cache system allows using SDRAm in burst mode (reduce extra cycle overhead (RAS/CAS cycle)).

A good way for implementation is a set of 2 registers, 1 for the address and the second for the data :
Writting the address register cause the prefetching of the memory area which contains the requested data. Then, if the read operation is requesed, the data will be present in the internal DPRAM. In this other case (for a write operation) just write in the corresponding register (DataReg). For a easier use, implement an auto-increment address register. Then when the address goes out the cached data, write the current buffer and prefetch the followed segment.

Good work

cs