| ??? 02/24/06 06:43 Read: times |
#110649 - practical consequence Responding to: ???'s previous message |
One practical consequence of the different "history"/buildup of CPLD and FPGA: as CPLDs are multiple PAL/GAL which is a huge programmable AND/OR array plus a handful of "macrocell" as the only place having registers/latches, they are not suited for sequential logic (i.e. requiring registers/latches), but very well suited for very wide input combinatorial logic (= address decoding)("glue logic", said somewhere above).
On the other hand, each of the many many small "cell" in FPGA contains a register/latch, hence a complex xombinatorial logic can be built; but wide input combinatorial logic might have serious timing problems (needs to chain a lot of "cells"). Jan Waclawek |
| Topic | Author | Date |
| FPGA/CPLD | 01/01/70 00:00 | |
| differences | 01/01/70 00:00 | |
| SRAM | 01/01/70 00:00 | |
| you don't | 01/01/70 00:00 | |
| Security | 01/01/70 00:00 | |
FPGA's were MMI's also ... | 01/01/70 00:00 | |
| copying | 01/01/70 00:00 | |
| Re: comparison | 01/01/70 00:00 | |
| Incorrect? | 01/01/70 00:00 | |
| No, however... | 01/01/70 00:00 | |
| about FPGA in 8052? | 01/01/70 00:00 | |
| In a way yes. | 01/01/70 00:00 | |
| i heard | 01/01/70 00:00 | |
| Low cost | 01/01/70 00:00 | |
| FPGA vs microcontroller | 01/01/70 00:00 | |
| Not necessarily | 01/01/70 00:00 | |
| You know it makes sense! | 01/01/70 00:00 | |
| yeah well | 01/01/70 00:00 | |
| Xilinx stuff | 01/01/70 00:00 | |
| Flash based | 01/01/70 00:00 | |
| Basic logic elements differ | 01/01/70 00:00 | |
| It seems... | 01/01/70 00:00 | |
| Consensus | 01/01/70 00:00 | |
| practical consequence | 01/01/70 00:00 | |
| Jan, Try reading this post | 01/01/70 00:00 |