| ??? 06/27/06 11:50 Read: times |
#119188 - Part of the i2c spec Responding to: ???'s previous message |
The pulse you refer to is detailed in the i2c specification. It is ACK/NACK. Yes, I can understand it will cause a problem if ignored! It is also used for the write cycle also! For a read, the master supplies the ACK/NACK (nack is usually used on the last byte to read),whereas for a write, the slave supplies the ACK/NACK.
Its nice to see the datasheets weren't lying to you! |
| Topic | Author | Date |
| note the pulse in 24C01~16 | 01/01/70 00:00 | |
| Part of the i2c spec | 01/01/70 00:00 | |
| no sign of I2C | 01/01/70 00:00 | |
| hoe about SMB | 01/01/70 00:00 | |
| Philps, I2C, SMBus, et al... | 01/01/70 00:00 | |
| TWI | 01/01/70 00:00 | |
| I2C in all but name | 01/01/70 00:00 | |
| Part of the i2c spec | 01/01/70 00:00 | |
| Part of the i2c spec | 01/01/70 00:00 | |
from the horses mouth | 01/01/70 00:00 |