The schematic vs. HDL discussion is interesting to me because parallels a similar situation that I've run into when writing software. While I can read and write C with the best of them, it's far more difficult for me to comprehend a piece of complicated logic in textual form, like this:

START Wake up
  REPEAT
    IF Hungry?\No\Yes
      IF Any new 8052.com mes- sages?\Yes\No
        WHILE For each message\More\Done
          Read it
          IF Have an inane question?\Yes\No
            Post a reply
            ENDIF
          ENDWHILE
      ELSE
        Start a five minute timer
        REPEAT
          Do something useful
          UNTIL Has timer expired?\Yes\No
        IF Tired from all that work?\Yes\No
          Take a nap
          ENDIF
        ENDIF
    ELSE
      Eat a handful of M&Ms
      ENDIF
    UNTIL Bedtime?\Yes\No
  END Go back to bed

than if it's presented in a graphical form, like this:



As Richard hints, maybe this an age thing, but I don't think so. I think that some people are just wired such that pictures make more sense to them. In any case, to indulge my own preference, I have a program that generates the graphical representation from the pseudocode, as shown above, and guarantees that the two are equivalent. This setup gives several benefits:

• I can quickly design the logic of my programs by typing pseudocode, with none of the mouse and GUI nonsense that would be required to create the flowcharts directly.
• I can quickly and easily determine if the logic is constructed the way I want, simply by inspecting the resulting flowcharts.
• If I'm working in a HLL, it's easy to reformat the pseudocode as comments and then use the result as a template for writing the acutal code. On the other hand, it's easier for me to write assembly language using the flowcharts as a guide.
• If I'm explaining the logic to someone else, they usually like the flowcharts better.
• Much to the amazement and delight of all concerned, some of the design documentation actually gets done before the implementation!

So to tie this in with the HDL vs. schematic debate, here's a question that may be so naive that it is stupid. But I'll ask it anyway: Aren't there tools that automatically generate guaranteed-equivalent schematic diagrams from HDL? If not, why not? It seems that if some hotdog piece of software can synthesize a chunk of logic from a chunk of HDL, it would be a minor matter for it to spit out a schematic diagram as part of the bargain.

-- Russ