| ??? 05/18/12 02:12 Read: times | #187405 - Other solutions Responding to: ???'s previous message | 
| Jason Arkwright said: ..implemented in a ATmega48 running overclocked at 32MHz, works great but for 8 bits resolution I can get up to 2KHz sine.
 If you are already in AVR, did you look at the XMEGAs ? Only a small jump from Mega48 in SW terms, and they have 12b DACS and plenty of RAM. Or, if you _really_ want high performance Sine saves, try something like this http://www.cirrus.com/en/produc...ey=CS47024 That has 108dB precision Audio DACS, and a DSP all in one package. One way to get higher precision, (smaller steps) in a Fixed Frequency generate, is to vary the samples per cycle. (that does need new table calculates for each frequency) If you assume a 1KHz sine from a 1000 sample scan, that same 1MHz rate can generate 999Hz with a 1001-baseline scan, and 1001 Hz with 999-baseline scan Give the scan more memory, for 10 whole cycles in 10k samples, and now you can resolve to 0.1Hz, with no jitter. | 
| Topic | Author | Date | 
| 256bit x 8 proms | 01/01/70 00:00 | |
| What frequency Sine wave & Clock ? | 01/01/70 00:00 | |
| Thank you | 01/01/70 00:00 | |
| DDS (Direct Digital Synthesis) | 01/01/70 00:00 | |
| digital sine wave | 01/01/70 00:00 | |
| uC sine generator | 01/01/70 00:00 | |
| DMA | 01/01/70 00:00 | |
| neither do I | 01/01/70 00:00 | |
| ARN | 01/01/70 00:00 | |
| 'F120 Series | 01/01/70 00:00 | |
| Other solutions | 01/01/70 00:00 | |
| 150nS access time is so long | 01/01/70 00:00 | |
| is that realy the case? | 01/01/70 00:00 | |
| Of course my solution | 01/01/70 00:00 | |
| Hmmm.., nice but... | 01/01/70 00:00 | |
| Those are actually PALs not CPLDs | 01/01/70 00:00 | |
| ATF750CL for PT clocks | 01/01/70 00:00 | |
| ATF750 | 01/01/70 00:00 | |
| ATF750C ? | 01/01/70 00:00 | |
| Yes, Jim You are exactly right. | 01/01/70 00:00 | |
| Can I suggest | 01/01/70 00:00 | |
| ATDH1150USB | 01/01/70 00:00 | |
| Update : ATDH1150VPC | 01/01/70 00:00 | |
| Thanks JIM   | 01/01/70 00:00 | 



