| ??? 10/23/05 21:01 Read: times |
#102787 - Drawbacks of Fig 6 Responding to: ???'s previous message |
The arrangement in fig 6 has variable settling time and variable output resistance, dependant on the input code value. The output would almost certainly need buffering, but you don't need a negative supply. |
| Topic | Author | Date |
| TLC7628 DAC | 01/01/70 00:00 | |
| Ref Connections | 01/01/70 00:00 | |
| RFBA is important current output of DAC | 01/01/70 00:00 | |
| Ok, which is better | 01/01/70 00:00 | |
| An OPamp is needed anyway | 01/01/70 00:00 | |
| Drawbacks of Fig 6 | 01/01/70 00:00 | |
Source impedance is constant | 01/01/70 00:00 |