I agree with Jan entirely. However, I'd like to add a note to this.

The notion of quoting a number of TTL loads that may be connected to a device is undoubtedly an outdated concept, and in today's world, it's actually rather misleading. Traditional TTL techonology is in its twilight years, giving way to vastly improved TTL variants that have more ideal characteristics, including increased input impedance. And, as Jan noted, there are other technologies, like HCT and ABT that are not really TTL-based, but still TTL-level compatible, that offer even better performance.

It is true that CMOS inputs have very high input impedances in their quiescent states. However, the gate in a PMOS or NMOS transistor has a non-trivial capacitance, which must effectively be charged or discharged with each logic transition. The bigger the transistor, and the larger its gate, the higher the capacitance, for basic reasons. In any case though, the power dissipation in CMOS electronics is roughtly proportional proportional to the switching frequency as a result of this capacitance. In addition, connecting more gate inputs to a gate output will result in the slew rate dropping on that net. Outside of the increased risk of missing timing requirements, presenting CMOS gate inputs with particularly low slew rate signals can result in very high transient power dissipation as the input hovers around V_M, in which both the PMOS pull-up and NMOS pull-down networks will be active.

So, in short, "TTL loads" is probably a term that shouldn't be used any more, and CMOS/other newer technologies, while much improved, are not necessarily a panacea.

--Sasha Jevtic