once the internal watchdog bites, there is no guarantee whatsoever that the uC will function correctly.

fron t6he datasheet
13.3. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.

What you need to do is to have a 'split' power supply: two diodes, one feeding a smallish capacitor with a bleeder resistor that supply an external watchdog connected to an uC interrupt, the other feeding a large capacitor supplying your uC. That way you can get some time after power fail where the uC has enough Vdd to save the values. If the internal supervisor resets before you have saved all, you are lost.

Erik