Today, there are more "accelerated" architectures around, roughly identified by the "oscillator clock per machine cycle" ratio (shortly, N-clocker, where N is this ratio).

The "classic" intel 8051/8052 (reincarnated e.g. as AT89C5x) is a 12-clocker.

There is a big family of 6-clockers, all members of the RD2 sub-family (Atmel, Philips, Winbond, SST), and most of the modern Atmel AT89Sxx. Usually, they come with a "switch" (a SFR bit or a programmable fuse or both), so you can switch them to "compatible" 12-clock mode (or this is the default mode).

Then there is a group of 4-clockers, lead by Dallas's legendary 80C320 (historically the first "accelerated" architecture), other types include some of the uPSDs by ST, the older of the Goal/Ramtron's Versa-s, and perhaps a few other.

Then there is the LPC9xx family from Philips which are 2-clockers.

Finally, the cream of creams are 1-clockers, lead by SiLabsd (ex-Cygnal), the newer Versa-s and quite a few other.

When it comes to machine cycle per instruction, there are 1-, 2- and 4-cycle instructions in the original 12-clocker '51 (the only 4-cycle instructions are DIV and MUL). The 6- and 2-clockers have the same machine cycle per instruction structure as the 12-clockers, so the timing on them is the same as on the original (scales linearly with the clock and clock/cycle ratio). The 4- and 1-clockers have different machine cycle per instruction structure, and they also differ from each other (although there are some general similarities, they tend to have the cycles per instruction related to the number of bytes the instruction has).

Complicating the picture more, some of the faster derivatives (and those are mostly the 4- and 1-clockers) have instruction prefetch queue plus a small cache to eliminate effect of prefetch flush at frequently repeating jumps, so it is hard or almost impossible to calculate their timing exactly. Plus, if they use external memory (usually data only), some of them insert - sometimes using a complicated scheme - one or more wait states, which also influences the overall timing.

An overview of clocking of some of the faster derivatives can be found [shameless self-advertisement]in my overview here[/shameless self-advertisement].

Jan Waclawek