I have written this sample code for transmitting and receiving a character to a CODEC using I2C port of a C8051F310 Micro-controller.
The write sequence is :

S - SLA+W - (A) - INCR+MAP - (A) - DATA1 - (A) - .... - DATAn - (A) - P

The read sequence is :

S - SLA+R - (A) - (DATA1) - A - .... - A - (DATAn) - NA - P

Where,

S       : Start condition
P       : Stop condition
(A)     : Ack received by the firmware
A       : Ack sent by the firmware
NA      : NAck sent by the firmware
SLA+W, SLA+R: SLave Address with Write/Read bit
DATAx   : data sent by the firmware
(DATAx) : data received by the firmware

The character is read and written using polling method:

; this program provides an example of how to configure the I2C Interface
; an internal 24500000hz internal oscillator is used as the system clock source.;
;-----------------------------------------------------------------------------


$include (c8051f310.inc); include register definition file.

;-----------------------------------------------------------------------------
; EQUATES
;-----------------------------------------------------------------------------

GREEN_LED   equ   P3.3; Green LED: '1' is ON	

SMB_MTSTA   equ   0xE0;(MT) start transmitted


; stack

stack       segment idata   ; declare stack segment
            rseg  stack
            ds    80h       ; reserve 128 bytes for stack


;-----------------------------------------------------------------------------
; byte definitions
;-----------------------------------------------------------------------------

receive_byte  equ 32h ; Received byte after Read operation

;-----------------------------------------------------------------------------
; reset and interrupt vector table
;-----------------------------------------------------------------------------

cseg at 0           
	     ljmp  main

             org   0bh
            ljmp  timer0_isr       ; timer0 overflow interrupt	
						                  
;-----------------------------------------------------------------------------
; main program code
;-----------------------------------------------------------------------------

pm33      segment  code                 ; declare code segment
            rseg  pm33                  ; select code segment
            using 0                     ; using register bank 0
;-----------------------------------------------------------------------------
; main subroutines
;-----------------------------------------------------------------------------
main:
            anl   pca0md, #not(040h)  ; clear watchdog enable bit
            mov   sp, #stack-1            ; init stack pointer
	    clr   a                       ; wait at least 1ms
            djnz  acc, $                  ;  wait 512us
            djnz  acc, $                  ;  wait 512us
						mov   r0,#07fh
clear_RAM:  mov @r0,#00
          djnz r0,clear_RAM; to clear the RAM bytes 00 to 7Fh								
	   call port_io_init; Initialize ports for SCL,SDA and P3.3 (LED)
	  mov  OSCICN,#083h ; internal oscillator					 
	  lcall timer_init ; timer initialisation
    	  lcall timer0_init; timer 0 initialisation		
    	  acall SMBus_Init ; Initialize SMBus				  lcall interrupts_init ; interrupts enable             
; Read the chip I.D and revision history byte (address 01)				
	  clr   GREEN_LED ; Initialize LED to OFF
        
					         
Loop2:      mov   R7, #03h; Code to Blink LED  		
Loop1:      mov   R6, #00h
Loop0:      mov   R5, #00h
            djnz  R5, $
            djnz  R6, Loop0
            djnz  R7, Loop1
            cpl   GREEN_LED; Toggle LED.
            call  transmit
	    call delay_20ms
	    call delay_20ms
	    call delay_20ms
	    call delay_20ms
	    call  receive
	    jmp   Loop2


;-----------------------------------------------------------------------------
; subroutines
;-----------------------------------------------------------------------------
port_io_init:
    ; P0.0  -  SDA (SMBus), Open-Drain, Digital
    ; P0.1  -  SCL (SMBus), Open-Drain, Digital
    ; P0.2  -  Unassigned,  Open-Drain, Digital
    ; P0.3  -  Unassigned,  Open-Drain, Digital
    ; P0.4  -  Unassigned,  Open-Drain, Digital
    ; P0.5  -  Unassigned,  Open-Drain, Digital
    ; P0.6  -  Unassigned,  Open-Drain, Digital
    ; P0.7  -  Unassigned,  Open-Drain, Digital

    ; P1.0  -  Unassigned,  Open-Drain, Digital
    ; P1.1  -  Unassigned,  Open-Drain, Digital
    ; P1.2  -  Unassigned,  Open-Drain, Digital
    ; P1.3  -  Unassigned,  Open-Drain, Digital
    ; P1.4  -  Unassigned,  Open-Drain, Digital
    ; P1.5  -  Unassigned,  Open-Drain, Digital
    ; P1.6  -  Unassigned,  Open-Drain, Digital
    ; P1.7  -  Unassigned,  Open-Drain, Digital
    ; P2.0  -  Unassigned,  Open-Drain, Digital
    ; P2.1  -  Unassigned,  Open-Drain, Digital
    ; P2.2  -  Unassigned,  Open-Drain, Digital
    ; P2.3  -  Unassigned,  Open-Drain, Digital
    ; P3.3  -  Unassigned,  Push-pull, Digital  
		                                 
    mov   XBR0,   #004h
    mov   XBR1,   #040h         ; Enable the Port I/O Crossbar
   orl   P3MDOUT,#08h          ; make LED pin output push-pull
    orl   P3MDIN, #08h          ; make LED pin input mode digital
    ret


 
;TIMER INITIALIZATON
timer_init:
    mov  TMOD,#002h ;Mode 2: 8-bit counter/timer with auto-reload
    mov  CKCON,#004h ;1: Counter/Timer 0 uses the system clock.   
    ret
;INTERRUPT INITIALIZATON
interrupts_init:    
setb et0 ; enable timer0	
setb ea  ; Enable global interrupts
ret
;TIMER0 INITIALIZATON for SMBus clock source of 100 kHz

timer0_init: mov  TH0, #0AFh;100khz is bit rate from clock source
	     ret


;SMBUS INITIALIZATON
SMBus_Init:  orl  SMB0CF,#080h ;SMBUS interface enabled
             setb tr0        ; Timer0 enabled		
             ret

;read sequence  
;S - SLA+W - (A) - INCR+MAP - (A) - P
;S - SLA+R - (A) - (DATA1) - A - P

RECEIVE:     push ACC 	; Preserve accumulator
            ;START  
	    clr STO
	    setb STA ; S        Initiate Transfer			
	    clr SI
	    jnb SI,$			
				
S1:      clr STA
	 mov SMB0DAT,#098h	; SLA+W			
	clr SI		
	jnb SI,$
        jnb ACK,$
				    

S2:      mov SMB0DAT,#0Dh ; INCR+MAP
	 clr SI
	 jnb SI,$
	 jnb ACK,$
						


S3:       setb STO   ;P; Setting STO to logic 1 causes a STOP condition to be transmitted 
            
	  setb STA         ;S 
	  clr SI
	  jnb SI,$			

S4:        clr STO
           clr STA
	   mov SMB0DAT,#099h ; SLA+R
	   clr SI
	   jnb SI,$
	   jnb ACK,$
						

S4_5:       clr SI            
	   jnb SI,$


S5:        mov  receive_byte,SMB0DAT ;DATA1
	   setb STO
            clr SI	
	   setb ACK	        
						
SMB_END:   pop ACC ; Restore accumulator
	   ret

transmit:    push ACC ; Preserve accumulator
            ;START  
	     clr STO
	     setb STA ; S        Initiate Transfer			
						
	    clr SI
	    jnb SI,$			
				
T1:         clr STA
	    mov SMB0DAT,#098h	; SLA+W			
	    clr SI		
	    jnb SI,$
	    jnb ACK,$
				    

T2:         mov SMB0DAT,#0Dh ; INCR+MAP
	    clr SI
STOPLOC:    jnb SI,$
	    jnb ACK,$

T5:         mov  SMB0DAT,#08H ;DATA1
	    clr SI
	    jnb SI,$
	    jnb ACK,$					
            setb STO
                   
						
TSMB_END:  pop ACC ; Restore accumulator
	   ret

delay_20ms:         push 00
                    push 01
                    mov r0,#255
delay_20ms_loop1:   mov r1,#255
delay_20ms_loop2:   djnz r1,delay_20ms_loop2
                    djnz r0,delay_20ms_loop1 
                    pop 01
                    pop 00
                    ret

timer0_isr: reti

end