Btw. I did not understand your example, please forgive my dumbness.

let me try - not to "forgive your dumbness" that is easy :), but to explain the example

if you have a project that averages, say, 128 readings of a timer you do not want any intefrerence of the timer during the readings. In such a case the 2% will lead to major errors. Thus you design it so that a reading that is intefered with get thrown away. If such a device is on a multidrop 485 bus it will have to throw away an awful lot of readings because there was an UART interrupt during the reading. Just visualize how often the master will send "do you want to send" at a time when all slaves just respond "no". If you have hardware address recognition you will only need to throw away the readings that get screwed up when the actual device is "asked".

As I said, this is not easy to explain in a condensed forn, I can give you examples that REALLY illustrates this, but only if you want to fly to RDU and see me do it on a whiteboard.

Erik