| ??? 05/16/07 21:31 Read: times |
#139402 - the counter is not 'a counter' Responding to: ???'s previous message |
quoting "the bible": In the “Counter” function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle.
I can see all kinds of 'synchronization problems' if you run close to the cycle time. I can not say this for sure, but do surmise that the 'counter' need see one low 'sample' and one high 'sample' to clock. This brings us down to 1MHz and then visulaize running e.g. 999kHz and figure the sampling. Erik |
| Topic | Author | Date |
| 8051 frequency meter. Interrupt question | 01/01/70 00:00 | |
| Formatted Code | 01/01/70 00:00 | |
| Thanks Jon | 01/01/70 00:00 | |
| No Problem - What about EA | 01/01/70 00:00 | |
| EA | 01/01/70 00:00 | |
| corrected code | 01/01/70 00:00 | |
| that is a pipe dream | 01/01/70 00:00 | |
| External hardware | 01/01/70 00:00 | |
| Why no more than 100K? | 01/01/70 00:00 | |
| the obvious way to do this is to use one timer as | 01/01/70 00:00 | |
| there is a 3rd byte | 01/01/70 00:00 | |
| no good | 01/01/70 00:00 | |
| assuming you can do the math... | 01/01/70 00:00 | |
| HUH | 01/01/70 00:00 | |
| And what? | 01/01/70 00:00 | |
| ... and ... | 01/01/70 00:00 | |
| Eh? | 01/01/70 00:00 | |
| the counter is not 'a counter' | 01/01/70 00:00 | |
| you should be on the safe side... | 01/01/70 00:00 | |
| who cares who 'wins' | 01/01/70 00:00 | |
| Continuation... | 01/01/70 00:00 | |
| now let\'s cheat | 01/01/70 00:00 | |
| Get something working first | 01/01/70 00:00 | |
| I diasagree | 01/01/70 00:00 | |
It's WORKING!! | 01/01/70 00:00 |