OK Roberto,

I didn't know that you just pass the border inside 8052 micro world.
The I/O space is now mapped in external RAM space, even if you want or not to access external RAM.
It doesn't matter for 8052 if he address one genuine I/O location or RAM cells.
You have to get used with this and forget /IORQ, /MREQ Z80 signals and C register placed on A7-A0.
If you want to access one particular I/O location, you have to put the I/O address
in DPTR register and then execute MOVX A, @DPTR for old IN A, (n) mnemonic.
The 80C390 will send DPL on port 1, DPH on port 2 and DPX on port 4 and
expected to receive the 8 switches input status on port 0.
If you want to sacrifice the wide external access space of 80C390 you can use straight the PCE3 signal
in order to drive /G of 244 octal buffer.
You will connect the 8 switches to the 244 buffer and link further the output of buffer to port 0 of 80C390.
Or could use demultiplexer like 74F138 enabled by PCEx and RD 80C390 signals.

I can give you more details if you can mention the board configuration (like amount of PROM bank used).

Yes, it is true using CE0-3 area as wr/rd too, when you will use the bootstrap loader and
place the program in RAM instead of EPROM or PROM, and using not only MOVC instruction in program memory area.
There are pleanty of possibility using 80C390 and I don't know if you choose the right
micro for start learning the 8031 family.
When i say that, I'm thinking about a lot setting in SFR area, that you have to take care.

Good luck anyway,