I haven't any direct experience with Atmel 805x's, nor is it on my immediate agenda to get any. I only have one Philips part in house. However, I doubt that an additional load of 5 pf, particularly if one intends to use a buffer in order to drive an external circuit and therefore designs for such usage, would make the oscillator misbehave if that typical 5 pF load were calculated into the load capacitance on the oscillator. That remains to be seen, of course. The faster devices have smaller cap's, so the 5 pf increase for one HCMOS or ACMOS gate will be a bigger proportion of that capacitance.

The oscillators on several of my 805x specimens, whether NMOS, HMOS, CHMOS, or CMOS seem to be pretty forgiving. I've had them start up just fine with load cap's exceeding twice the recommended value, and considerably more in some cases, as well as some less than half the recommended value. This hasn't been thoroughly and rigorously tested, though, nor has it been discussed with any sort of rigor by any of the manufacturers since CMOS became the "run-of-the-mill" technology.

That, in part, is why I'm interested in seeing a cursory survey of results that are observed.

The oscillator on SiLabs parts isn't entirely relevant anyway, in this case, is it? They often use a PLL to manipulate the oscillator into the clock that they require.

RE