I'm trying to figure out the interrupt enable bits for the comparators on the Silicon Labs C8051F120. Figure 10.4 of the data sheet shows that the CPT0MD register contains a couple of bits, CP0RIE and CP0FIE that look like they are supposed to enable interrupts resulting from rising and falling edges, respectively on the output from Comparator 0. That all seems great, except that the data sheet also shows that the EIE1 register contains two bits, ECP0R and ECP0F that apparently do exactly the same thing.

I can't find anything in the data sheet that explains why there are two sets of interrupt enable bits. When do you use CP0RIE/CP0FIE and when do you use ECP0R/ECP0F?

I played around with the Configuration Wizard 2 a little bit, hoping to answer this question, and saw that it very carefully sets up ECP0R/ECP0F, but doesn't do anything very intelligent with CP0RIE/CP0FIE. This makes me guess that maybe CP0RIE/CP0FIE are not present in the C8051F120 and that maybe Figure 10.4 of the data sheet is wrong.

But I don't like guessing. Can anybody point to some documentation that explains this?

Thanks,

-- Russ

PS: I'll post this question to the SI Labs forum in just a minute, and report back here if anybody there has the answer.