First, the routine is likely clocking the I2C bus too fast (those SCLK pulse are normally 100Khz or 400Khz), but that's a secondary issue. The bus master sets SDATA hi but still has to sample the SDATA line to ensure the slave device is not holding it low in a wait state. Remember, SCLK and SDATA are open collector, so any bus device can pull it low into a busy state.

Not sure what your hardware looks like, but my guess is the routine is trying to clear the bus with the last statement. The value of SDATA is thrown away, but that's an error as it has to know if the line is still low (busy).

Combined with the too fast clock I'd say the routine was not tested with real hardware. I ran into the same problem just last week, debugging a similar routine from code in a reference design.
Jack Peacock