You can build dual-port RAM within the Configurable System Logic (CSL) cells in a Triscend device.

If one side of the dual-port RAM connects to the internal system bus, then a 256x8 dual-port RAM consumes just 256 cells.

The Triscend FastChip library has a dual-port RAM module, as well as modules for building FIFOs.

Similarly, the on-chip DMA controller allows you to build buffers using the on-chip RAM, which might eliminate the need for dual-port RAM altogehter.