If you download the Altera package, it contains a Verilog and a VHDL
compilers for free. You could implement the project on FPGAs with
a sufficiently big number of macrocells (2K to 5K cells). They are not
cheap !

If your project is a system on a chip component, the Triscend E5 family
is certainly a better way. You get a core 8051 with 0.5 to 4K macrocells
for your project implementation, at a low cost, all in the same chip.

You could find VHDL descriptions of 8051 chip (mainly behavioural) at
several sites in Europe universities :

Hamburg, Strasbourg, Erlangen and Wien.

Best regards,

J. M.