| ??? 05/27/08 14:22 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#155154 - A Simple Attenuator Responding to: ???'s previous message |
If a simple attenuator is suitable for your design then a circuit like this would do the trick. I threw this together very quickly with LTSpice to show the concept.
With a sine wave excitation input that has a peak-peak swing of -10V to +10V the output of the attenuator (for the resistor values shown above) is about 1mV to 2.49V.
So some minor tweaking may be required if you want -10V -> 0V and +10V -> 2.5V exactly. For the circuit shown the VREF source is sourcing current up to about 1mA when the VIN is at -10V and so this needs to be taken into account when selecting the VREF component. Sometimes it is desirable to buffer the VREF from the regulator with a unity gain buffer to the attenuator. Note that an attenuator like this puts a non-symmetric current draw on the signal source and is one of the reasons an opamp input may be desirable. Michael Karas |
| Topic | Author | Date |
| ADC of Silabs MCU | 01/01/70 00:00 | |
| At best the SiLabs A/D.... | 01/01/70 00:00 | |
| A Simple Attenuator | 01/01/70 00:00 | |
| Tweaking... | 01/01/70 00:00 | |
| Further tweaking.. | 01/01/70 00:00 | |
| yes | 01/01/70 00:00 | |
| I had that coming.. | 01/01/70 00:00 | |
| Drop the Trim | 01/01/70 00:00 | |
| 100% practical with theory | 01/01/70 00:00 | |
| For your A/D Subsystem.... | 01/01/70 00:00 | |
| buffer op-amp | 01/01/70 00:00 | |
| Chosen Op-Amp : CA5420A | 01/01/70 00:00 | |
| Settling time? | 01/01/70 00:00 | |
| My signal is a slowly varying one | 01/01/70 00:00 | |
settling time | 01/01/70 00:00 | |
| internal reference specified from 2.36 to 2.48 V! | 01/01/70 00:00 | |
| do not calibrate if you can avoid it | 01/01/70 00:00 |



