It is possible to get SPI memories to support direct execution of code but it takes two very important things.

A) The processor that will be executing the code must expose a parallel bus interface including instruction address bus, data bus and read/write controls.

B) You add a hardware sequencer designed into a small FPGA or medium CPLD that translates the parallel processor bus into the necessary serial interface and commands to run the SPI memory.

SPI flash chips are available today with serial interfaces up towards 70 MHz so the translation process could support the processor bus at a couple of MHz. This would be roughly equivalent performance to an older 6 clocker 12 MHz 8051 part.

Another way to support direct execution is to build a small cache inside the FPGA that can hold say 256 bytes of data from the SPI Flash which is then filled using a block read which is the most efficient serial Flash reading method. The attached MCU executes from the cache memory until there is need for code from a different page at which time the cache is re-filled with new code image data.

Since the typical 8051 type processor does not have a WAIT/ pin you would have to run the MCU at a clock frequency commensurate with the design of the CPLD and the SPI shift rate. The caching system described could be used at full bus speed of the MCU until when the cache misses and the the MCU clock could be stopped momentarily.

There are devices on the market that use SPI Flash devices for code storage. One such device is in the part family described here: http://www.serverengines.com/products/...ement.html which can direct execute from SPI Flash.

There are other devices in the market now which also support various types of execution from SPI Flash. The ICH9 device from Intel for example supports the use of SPI Flash for a PC system BIOS. Initial BIOS execution on systems of this type run directly from the SPI flash until enough code us loaded to initialize RAM and allow execution of the BIOS image moved to RAM. You can read more about the Intel part here (even though it is not very applicable to an 8051 system): http://www.intel.com/design/ch...316972.htm

Michael Karas