I also cannot see support for the delay needed between successive write cycles to take care of the internal write time of the EEPROM array. For normal devices of the AT24C512 this time requires a delay of 10 milliseconds after the STOP is sent on the I²C bus to the part.

The part does support writing of up to 128 bytes in sequence that can then be written in the PAGE mode. I do not see that the shown code provides support for comprehending that the address sent to the AT24C512 in PAGE write mode will roll over at the end of a page boundary of 128 bytes back to the beginning of the same page.

Both of these issues will cause the device to respond in unexpected ways of you try to cram additional write or read cycles to the part while the device is in the midst of the internal write time of 10 milliseconds.

These particular characteristics of the device are of course described in detail in the data sheet available at the Atmel web site.

Michael Karas