After an external memory cycle, P0 is set to 0FFh (i.e. all pins floating - it's an open collector in that moment), and P2 regains its previous state (as having been written to the P2 SFR).

Yes, if the corresponding bits in P3 SFR are 1.

With such a "mixed" mode, while possible, a mild caveat also might be, that while in the "true" external memory cycles both P2 and P0 are driven strongly to both 0 and 1; in the "port mode" P0 is open collector only, and P2 has that intel-ish quasi-bidirectional property.

JW