Now, I am entirely unsure of how it's supposed to work, but it seems to me that if you externally register the P2 and P0 data on the rising edge of ALE, those external registers (e.g. 74HC273) will preserve the port values for you. This may not work in the same way on all 805x versions.

I've had no luck at all getting precise spec's from MAXIM on their DS89C4x0 chips, particularly when using their so-called Page Modes for external memory bus access, that reflect what is supposed to happen on those ports when operating in certain ways, but it seems to me that the spec's for nearly any 805x with internal code space pretty clearly suggest that the ports are useable as ports, regardless of what is externally attached, IF pullup resistors are provided on P0.

Given that fact, when one does execute a MOVX instruction the addresses ultimately appear during ALE on ports 0 and 2, and they presumably persist on those ports throughout the external bus cycle. If, therefore, you're using an external i8255 that's memory-mapped, i.e. uses nWR and nRD to drive the data path, and the external bus addresses to steer the data path, you should have no difficulty operating your external IDE interface in that mode. If you use those ports (P0 and P2) to "talk" to an external multi-byte device, e.g. a 12-bit parallel-interfaced ADC, you should be able to read it via those ports, provided the external data path hardware is correctly steered and enabled. Using P3 to manage that data path is perfectly reasonable, provided you've set the P3 port latch to 0xFF beforehand.

The weakness in using 805x in this way is in that it has no way of synchronizing with external processes that aren't either slow enough to allow bitwise control, e.g. via P3 as has been suggested, or fast enough to respond to nWR and nRD at the rate at which the MCU is operating. If the ADC is "fast," then, depending on the ADC, there's risk that its output may change between reads of the byte-wide ports, unless one registers its output externally.

My reading of the family spec's suggests that the ports P0 and P2 function as ports whenever an external memory cycle is not in progress. That will, I believe, be most of the time so long as all code space is internal. I would caution, however, that this can vary considerably with the many 805x-scions that have become available, particularly those that have "special" operating modes such as those "page modes" offered by the Maxim/Dallas MCU's.

RE