| ??? 01/08/09 01:44 Read: times |
#161370 - Very Good Point... Responding to: ???'s previous message |
RE makes a very good point here. Dividing down the CPU frequency should completely eliminate any count accumulation error due to possible inaccuracy of the CPU crystal or resonator. If the output of the divide down chain is done carefully with a synchronous scheme as opposed to using some ripple carry type counter it should be possible to present a signal to the T0 input that will never have an uncertainty of more than 1 count. This can make for an extremely valuable software test bed to iron out any issues with how the software enabled counter measuring system functions.
Michael Karas |
| Topic | Author | Date |
| Frequency (Event) Counter Problem | 01/01/70 00:00 | |
| less than 1% error | 01/01/70 00:00 | |
| Error % is incremental. | 01/01/70 00:00 | |
| ;STARTING BOTH THE TIMERS AT THE SAME TIME | 01/01/70 00:00 | |
| Less variations in TL0 but still error | 01/01/70 00:00 | |
| I do not know, but | 01/01/70 00:00 | |
| CRO Frequency Measurement | 01/01/70 00:00 | |
| Better But Still An Issue | 01/01/70 00:00 | |
| How stabile is your signal source? | 01/01/70 00:00 | |
| Very Good Point... | 01/01/70 00:00 | |
| Easier if 89c52 is used | 01/01/70 00:00 | |
| How stabile is your signal source? | 01/01/70 00:00 | |
NE555 is popular but not a precision device | 01/01/70 00:00 |