Interrupts are possible in this config as well. You make the ROM code store in the first RAM addresses (typically 8000 hex) the actual address of the bootcodes ISRs before enabling interrupts. The interrupt location(e.g. 3) the contains an indirect jump (mov dptr,# - clr a - jmp @a+dptr) to what 800n point to. The initializer of the RAM code will disable interrupts, write the new ISR addresses to 8000-800n and reenable the interrupts.

Yes, it is possible

Erik