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12/17/01 09:10
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#17716 - RE: fault tolerant sbc design
At first, you must make your design reliable. Since it make no sense to use a couple of CPUs, if all these unreliable.
Also for such redundant systems an odd number was needed (3, 5, ...) to make a majority decision.
Typically also different CPUs and different languages used.

But now some hints to get reliability at first:

- deliver a clean power supply voltage

- prefer internal code memory, since many times better proofed against any kind of EMI (for extreme reliability factory programmed ROM used instead Flash)

- deliver an excellent power on reset
(mostly the MAXIM parts known as reliable)

- use an always enabled watchdog (external, since most internal are sleeping after power on and possible do be disabled).

- protect, debounce all inputs and outputs (supressor diodes, debouncing software)

- also the pcb design and the housing are importand.


I think, there are many other points.
And forget not to make the software reliable. E.g. on state machines decode every state, also such which looking impossible to be reached.


Peter

List of 6 messages in thread
TopicAuthorDate
fault tolerant sbc design            01/01/70 00:00      
RE: fault tolerant sbc design            01/01/70 00:00      
RE: fault tolerant sbc design            01/01/70 00:00      
RE: fault tolerant sbc design            01/01/70 00:00      
RE: fault tolerant sbc design            01/01/70 00:00      
RE: fault tolerant sbc design            01/01/70 00:00      

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