There is no way the IIC bus can allow simultaneous access (which is what you are describing). You must leave gaps in the IIC access by the 2 processors and "hope" the other does its thing in the gap.
Another cure is to tie the 2 processors together with 2 wires, for the sake of argument let us use p1.1 and p1.2. When processor #1 wants to write it examines p1.2 for high and when so, pulls p1.1 low and does its thing, then set p1.1 high. Same (bit reversed) for processor #2.

Happy hollidays,

Erik