Hi Simon,

I think that the problem with third priority level interrupt should be reflected from another point of view : Indeed, applications requires the third level ?
There are too many interrupts that we must to take care and are not enough two priority level and an inherent natural priority on each level in order to be solved?
Which interrupt should have highest (the third) privilege than others ? Which purpose, too ?

But before looking at the code proposed by Philips at the end of family architecture guide, please allow me a small digression.
Lets start with one derivative from MCS51 family; I call 80C390, which has three hardware available priority level, by default. The lower two are inherited from MCS51, the highest third is reserved only for PFI (Power Fail Interrupt).
The internal 80C390's band-gap voltage reference sets a precise reset threshold at which occurence an optional early warning Power Fail could be generated, if enabled. This kind of interrupt has its own enable bit EPFI on WDCON.5, but it couldn't be inhibit by global interrupt enable EA bit.
That is, it behaves like old NMI (NonMascableInterrupt). Well almost, since PFI could be inhibit, which is not the case with NMI.
The story goes further to MCS51 derivative made by Philips which provides four levels on-chip hardware by introducing IPH SFR #B7H.

As much as the number of interrupt sources increases, much obvious the needs of more than two interrupts levels.
It will be not so nice to solve our needs in software due the increase of the response time. But we can't have it all.

However, what means third priority level interrupt on a two priority level basis ?
Lets go back to Philips code and suppose we have set Timer 0 and Serial Port interrupt at first level, lowest priority.
The rest of interrupt sources, External 1, External 0 and Timer 1 are set to second level, highest priority.
Timer 2 will not request interrupt since is selected as baud rate generator. As you can see, we are dealing with standard 8052.
OK, lets suppose we have Timer 0 interrupt in progress and Timer 1 interupt request. Since a low-priority interrupt can be interrupted by a high-priority interrupt, the Timer 1 interrupt will be serviced.
What we have until now: Timer 0 interrupt in pending, Timer 1 interrupt running.
Oopps ! Now is coming External 0 interrupt request. Even if this kind of interrupt has the highest priority, she received this privilege only within level as internal polling results and only when occurs simultaneously.
How the system behave ? The External 0 interrupt will be serviced only after Timer 1 routine finishes with RETI. But that is what we don't want !.
Can you solve the above situation with two priority level interrupt ?:
-External 0 request will break both Timer 1 and Timer 0 interrupt routines, no matter which one is in progress.
-Timer 1 will break Timer 0 interrupt routine in progress.
I know you'll say that during timer 1 interrupt routine you can poll the External 0 interrupt flag. But wouldn't be too nice.
It's true that within each priority level is a second priority structure determined by the polling sequence.
But the polling sequence is only used to resolve simultanous request of the same priority level.

Could the Philips code do that ?

YES.

;Timer0 has on-chip hardware lowest priority level interrupt
;Serial has on-chip hardware lowest priority level interrupt
;External 1 has on-chip hardware higher priority level interrupt
;Timer 1 has on-chip hardware higher priority level interrupt
;External 0 has software highest priority level interrupt

MASK equ 91H

ORG 0000H
AJMP Start

ORG 0003H
AJMP Extern0

ORG 000BH
AJMP Timer0

ORG 0013H
AJMP Extern1

ORG 001BH
AJMP Timer1

ORG 0023H
AJMP Serial

Extern0:
;do what you want for highest priority get by software
RETI

Timer0:
;do what you want here
RETI

Extern1:
PUSH IE
MOV IE, #MASK
CALL Label
;do what you want here
POP IE
RET
Label: RETI

Timer1:
PUSH IE
MOV IE, #MASK
CALL Label
;do what you want here
POP IE
RET

Serial:
;do what you want here
RETI

Start:
MOV IP, #0DH
MOV IE, #9FH
;do what you want here

END

Happy New Year !