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???
08/02/11 20:33
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 		 #183154 - Someday you will learn...
Responding to: ???'s previous message
Someday you will learn what a bad idea it is to have an ISR that uses the registers as setup by the mainline code. You would be well advised to setup the ISR as a state machine and have it manage a transfer via your bit-banged I/O using a couple of global variables.

Michael Karas


List of 30 messages in thread
TopicAuthorDate
bit banging program touble            01/01/70 00:00      
   why?            01/01/70 00:00      
      i need a second serial port            01/01/70 00:00      
         something like this , without any warranty :            01/01/70 00:00      
         a good start would be ...            01/01/70 00:00      
            only 3 'U's are commingout of 100            01/01/70 00:00      
               Separate the characters and look with scope            01/01/70 00:00      
                  finally it worked            01/01/70 00:00      
                     uart receiver in software            01/01/70 00:00      
   No I/O or No Timing            01/01/70 00:00      
      "No I/O or No Timing"            01/01/70 00:00      
   Someday you will learn...            01/01/70 00:00      
      this isnt the actual code            01/01/70 00:00      
         Well then another lesson to learn...            01/01/70 00:00      
   Assembler Manual will help you            01/01/70 00:00      
      assembler manual?            01/01/70 00:00      
   Data is 8 Bit??            01/01/70 00:00      
   Bit width timing and timer TH0,TL0 Values            01/01/70 00:00      
      checked values for TH0 and TL0            01/01/70 00:00      
         keil baud rate Calculator not for bit bang            01/01/70 00:00      
   LSB first            01/01/70 00:00      
   now reception....            01/01/70 00:00      
      1) din = din >> 1            01/01/70 00:00      
         working at 1200 baud            01/01/70 00:00      
            delayRS()            01/01/70 00:00      
               why do i have to sample stop bit            01/01/70 00:00      
                  Need not, but should            01/01/70 00:00      
                  because            01/01/70 00:00      
                     Much to a real UART            01/01/70 00:00      
                  1.5 bit delay            01/01/70 00:00      

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